;; Function f (f) starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 7 n_edges 8 count 8 ( 1.1) f Dataflow summary: ;; invalidated by call 0 [$0] 1 [$1] 2 [$2] 3 [$3] 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 12 [$12] 13 [$13] 14 [$14] 15 [$15] 24 [$24] 25 [$25] 26 [$26] 27 [$27] 32 [$f0] 33 [$f1] 34 [$f2] 35 [$f3] 36 [$f4] 37 [$f5] 38 [$f6] 39 [$f7] 40 [$f8] 41 [$f9] 42 [$f10] 43 [$f11] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 52 [$f20] 53 [$f21] 54 [$f22] 55 [$f23] 64 [hi] 65 [lo] 66 [] 67 [$fcc0] 68 [$fcc1] 69 [$fcc2] 70 [$fcc3] 71 [$fcc4] 72 [$fcc5] 73 [$fcc6] 74 [$fcc7] 75 [] 76 [$cprestore] 176 [$ac1hi] 177 [$ac1lo] 178 [$ac2hi] 179 [$ac2lo] 180 [$ac3hi] 181 [$ac3lo] ;; hardware regs used 28 [$28] 29 [$sp] 77 [$arg] 78 [$frame] ;; regular block artificial uses 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] ;; eh block artificial uses 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] ;; entry block defs 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 25 [$25] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 77 [$arg] 78 [$frame] 79 [$fakec] ;; exit block uses 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 78 [$frame] 79 [$fakec] ;; regs ever live 2[$2] 4[$4] 5[$5] 6[$6] 7[$7] 8[$8] 9[$9] 29[$sp] 31[$31] 79[$fakec] ;; ref usage r0={1d} r1={1d} r2={2d,2u} r3={1d} r4={3d,2u} r5={3d,2u} r6={3d,2u} r7={2d,1u} r8={2d,1u} r9={2d,1u} r10={2d} r11={2d} r12={1d} r13={1d} r14={1d} r15={1d} r24={1d} r25={2d} r26={1d} r27={1d} r28={1d,6u} r29={1d,7u} r30={1d,6u} r31={2d,1u} r32={1d} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={2d} r45={2d} r46={2d} r47={2d} r48={2d} r49={2d} r50={2d} r51={2d} r52={1d} r53={1d} r54={1d} r55={1d} r64={1d} r65={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d,5u} r78={1d,6u} r79={2d,3u} r176={1d} r177={1d} r178={1d} r179={1d} r180={1d} r181={1d} r234={2d,1u} r250={2d,4u} r257={1d,2u} r262={1d,1u} r264={1d,4u} r265={1d,2u} r266={1d,1u} r267={1d,1u} r268={1d,1u} r269={1d,1u} r270={1d,1u} r271={1d,1u} r272={1d,1u} r273={1d,1u} r275={1d,1u} r277={1d,1u} r278={1d,1u} r279={1d,1u} r280={1d,1u} r281={1d,1u} r282={1d,1u} r283={1d,1u} r284={1d,1u} r285={1d,1u} r287={1d,2u} r288={1d,1u} r289={1d,1u} ;; total ref usage 203{122d,81u,0e} in 39{38 regular + 1 call} insns. ;; Reaching defs: sparse invalidated dense invalidated 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 87, 88, 89, 90, 91, 92 0[0,1] 1[1,1] 2[2,2] 3[4,1] 4[5,3] 5[8,3] 6[11,3] 7[14,2] 8[16,2] 9[18,2] 10[20,2] 11[22,2] 12[24,1] 13[25,1] 14[26,1] 15[27,1] 24[28,1] 25[29,2] 26[31,1] 27[32,1] 28[33,1] 29[34,1] 30[35,1] 31[36,2] 32[38,1] 33[39,1] 34[40,1] 35[41,1] 36[42,1] 37[43,1] 38[44,1] 39[45,1] 40[46,1] 41[47,1] 42[48,1] 43[49,1] 44[50,2] 45[52,2] 46[54,2] 47[56,2] 48[58,2] 49[60,2] 50[62,2] 51[64,2] 52[66,1] 53[67,1] 54[68,1] 55[69,1] 64[70,1] 65[71,1] 66[72,1] 67[73,1] 68[74,1] 69[75,1] 70[76,1] 71[77,1] 72[78,1] 73[79,1] 74[80,1] 75[81,1] 76[82,1] 77[83,1] 78[84,1] 79[85,2] 176[87,1] 177[88,1] 178[89,1] 179[90,1] 180[91,1] 181[92,1] 234[93,2] 250[95,2] 257[97,1] 262[98,1] 264[99,1] 265[100,1] 266[101,1] 267[102,1] 268[103,1] 269[104,1] 270[105,1] 271[106,1] 272[107,1] 273[108,1] 275[109,1] 277[110,1] 278[111,1] 279[112,1] 280[113,1] 281[114,1] 282[115,1] 283[116,1] 284[117,1] 285[118,1] 287[119,1] 288[120,1] 289[121,1] ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d7(4){ }d10(5){ }d13(6){ }d15(7){ }d17(8){ }d19(9){ }d21(10){ }d23(11){ }d30(25){ }d33(28){ }d34(29){ }d35(30){ }d37(31){ }d51(44){ }d53(45){ }d55(46){ }d57(47){ }d59(48){ }d61(49){ }d63(50){ }d65(51){ }d83(77){ }d84(78){ }d86(79){ }} ;; bb 0 artificial_uses: { } ;; lr in ;; lr use ;; lr def 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 25 [$25] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live in ;; live gen 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 25 [$25] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live kill ;; rd in (0) ;; rd gen (24) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86 ;; rd kill (46) 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 29, 30, 33, 34, 35, 36, 37, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 83, 84, 85, 86 ;; lr out 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live out 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] ;; rd out (24) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86 ( 0 )->[2]->( 3 6 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u0(28){ d33(bb 0 insn -1) }u1(29){ d34(bb 0 insn -1) }u2(30){ d35(bb 0 insn -1) }u3(77){ d83(bb 0 insn -1) }u4(78){ d84(bb 0 insn -1) }} ;; lr in 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] ;; lr use 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] ;; lr def 234 264 265 266 267 268 269 270 ;; live in 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live gen 234 264 265 266 267 268 269 270 ;; live kill ;; rd in (24) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86 ;; rd gen (8) 93, 99, 100, 101, 102, 103, 104, 105 ;; rd kill (9) 93, 94, 99, 100, 101, 102, 103, 104, 105 ;; lr out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 234 264 265 266 267 268 269 ;; live out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 234 264 265 266 267 268 269 ;; rd out (32) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 93, 99, 100, 101, 102, 103, 104, 105 ;; UD chains for artificial uses ;; reg 28 { d33(bb 0 insn -1) } ;; reg 29 { d34(bb 0 insn -1) } ;; reg 30 { d35(bb 0 insn -1) } ;; reg 77 { d83(bb 0 insn -1) } ;; reg 78 { d84(bb 0 insn -1) } ;; UD chains for insn luid 0 uid 40 ;; reg 4 { d7(bb 0 insn -1) } ;; UD chains for insn luid 1 uid 41 ;; reg 5 { d10(bb 0 insn -1) } ;; UD chains for insn luid 2 uid 42 ;; reg 6 { d13(bb 0 insn -1) } ;; UD chains for insn luid 3 uid 43 ;; reg 7 { d15(bb 0 insn -1) } ;; UD chains for insn luid 4 uid 44 ;; reg 8 { d17(bb 0 insn -1) } ;; UD chains for insn luid 5 uid 45 ;; reg 9 { d19(bb 0 insn -1) } ;; UD chains for insn luid 6 uid 51 ;; reg 264 { d99(bb 2 insn 40) } ;; reg 265 { d100(bb 2 insn 41) } ;; UD chains for insn luid 8 uid 52 ;; reg 270 { d105(bb 2 insn 51) } ( 2 )->[3]->( 4 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u14(28){ d33(bb 0 insn -1) }u15(29){ d34(bb 0 insn -1) }u16(30){ d35(bb 0 insn -1) }u17(77){ d83(bb 0 insn -1) }u18(78){ d84(bb 0 insn -1) }} ;; lr in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 264 265 266 267 268 269 ;; lr use 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 264 265 266 267 ;; lr def 250 257 262 271 272 273 287 288 289 ;; live in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 264 265 266 267 268 269 ;; live gen 250 257 262 271 272 273 287 288 289 ;; live kill ;; rd in (32) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 93, 99, 100, 101, 102, 103, 104, 105 ;; rd gen (9) 96, 97, 98, 106, 107, 108, 119, 120, 121 ;; rd kill (10) 95, 96, 97, 98, 106, 107, 108, 119, 120, 121 ;; lr out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 250 257 262 264 268 269 288 289 ;; live out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 250 257 262 264 268 269 288 289 ;; rd out (41) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 93, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 119, 120, 121 ;; UD chains for artificial uses ;; reg 28 { d33(bb 0 insn -1) } ;; reg 29 { d34(bb 0 insn -1) } ;; reg 30 { d35(bb 0 insn -1) } ;; reg 77 { d83(bb 0 insn -1) } ;; reg 78 { d84(bb 0 insn -1) } ;; UD chains for insn luid 0 uid 54 ;; reg 265 { d100(bb 2 insn 41) } ;; UD chains for insn luid 1 uid 55 ;; reg 257 { d97(bb 3 insn 54) } ;; reg 264 { d99(bb 2 insn 40) } ;; UD chains for insn luid 2 uid 56 ;; reg 271 { d106(bb 3 insn 55) } ;; UD chains for insn luid 3 uid 57 ;; reg 272 { d107(bb 3 insn 56) } ;; UD chains for insn luid 4 uid 58 ;; reg 273 { d108(bb 3 insn 57) } ;; UD chains for insn luid 6 uid 103 ;; reg 264 { d99(bb 2 insn 40) } ;; UD chains for insn luid 7 uid 62 ;; reg 266 { d101(bb 2 insn 42) } ;; reg 287 { d119(bb 3 insn 103) } ;; UD chains for insn luid 8 uid 64 ;; reg 267 { d102(bb 2 insn 43) } ;; reg 287 { d119(bb 3 insn 103) } ( 4 3 )->[4]->( 4 5 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u30(28){ d33(bb 0 insn -1) }u31(29){ d34(bb 0 insn -1) }u32(30){ d35(bb 0 insn -1) }u33(77){ d83(bb 0 insn -1) }u34(78){ d84(bb 0 insn -1) }} ;; lr in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 250 257 262 264 268 269 288 289 ;; lr use 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 250 262 268 288 289 ;; lr def 250 275 277 278 279 ;; live in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 250 257 262 264 268 269 288 289 ;; live gen 250 275 277 278 279 ;; live kill ;; rd in (46) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 93, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 119, 120, 121 ;; rd gen (5) 95, 109, 110, 111, 112 ;; rd kill (6) 95, 96, 109, 110, 111, 112 ;; lr out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 250 257 262 264 268 269 288 289 ;; live out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 250 257 262 264 268 269 288 289 ;; rd out (45) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 93, 95, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 119, 120, 121 ;; UD chains for artificial uses ;; reg 28 { d33(bb 0 insn -1) } ;; reg 29 { d34(bb 0 insn -1) } ;; reg 30 { d35(bb 0 insn -1) } ;; reg 77 { d83(bb 0 insn -1) } ;; reg 78 { d84(bb 0 insn -1) } ;; UD chains for insn luid 0 uid 63 ;; reg 250 { d96(bb 3 insn 47) d95(bb 4 insn 69) } ;; reg 288 { d120(bb 3 insn 62) } ;; UD chains for insn luid 1 uid 65 ;; reg 250 { d96(bb 3 insn 47) d95(bb 4 insn 69) } ;; reg 289 { d121(bb 3 insn 64) } ;; UD chains for insn luid 2 uid 66 ;; reg 277 { d110(bb 4 insn 65) } ;; UD chains for insn luid 3 uid 67 ;; reg 268 { d103(bb 2 insn 44) } ;; reg 278 { d111(bb 4 insn 66) } ;; UD chains for insn luid 4 uid 68 ;; reg 275 { d109(bb 4 insn 63) } ;; reg 279 { d112(bb 4 insn 67) } ;; UD chains for insn luid 5 uid 69 ;; reg 250 { d96(bb 3 insn 47) d95(bb 4 insn 69) } ;; UD chains for insn luid 6 uid 71 ;; reg 250 { d95(bb 4 insn 69) } ;; reg 262 { d98(bb 3 insn 58) } ( 4 )->[5]->( 6 ) ;; bb 5 artificial_defs: { } ;; bb 5 artificial_uses: { u47(28){ d33(bb 0 insn -1) }u48(29){ d34(bb 0 insn -1) }u49(30){ d35(bb 0 insn -1) }u50(77){ d83(bb 0 insn -1) }u51(78){ d84(bb 0 insn -1) }} ;; lr in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 257 264 269 ;; lr use 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 257 264 ;; lr def 234 280 281 282 ;; live in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 257 264 269 ;; live gen 234 280 281 282 ;; live kill ;; rd in (45) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 93, 95, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 119, 120, 121 ;; rd gen (4) 94, 113, 114, 115 ;; rd kill (5) 93, 94, 113, 114, 115 ;; lr out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 234 269 ;; live out 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 234 269 ;; rd out (48) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 94, 95, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 119, 120, 121 ;; UD chains for artificial uses ;; reg 28 { d33(bb 0 insn -1) } ;; reg 29 { d34(bb 0 insn -1) } ;; reg 30 { d35(bb 0 insn -1) } ;; reg 77 { d83(bb 0 insn -1) } ;; reg 78 { d84(bb 0 insn -1) } ;; UD chains for insn luid 0 uid 73 ;; reg 264 { d99(bb 2 insn 40) } ;; UD chains for insn luid 1 uid 74 ;; reg 257 { d97(bb 3 insn 54) } ;; reg 280 { d113(bb 5 insn 73) } ;; UD chains for insn luid 2 uid 75 ;; reg 281 { d114(bb 5 insn 74) } ;; UD chains for insn luid 3 uid 76 ;; reg 282 { d115(bb 5 insn 75) } ( 2 5 )->[6]->( 1 ) ;; bb 6 artificial_defs: { } ;; bb 6 artificial_uses: { u57(28){ d33(bb 0 insn -1) }u58(29){ d34(bb 0 insn -1) }u59(30){ d35(bb 0 insn -1) }u60(77){ d83(bb 0 insn -1) }u61(78){ d84(bb 0 insn -1) }} ;; lr in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 234 269 ;; lr use 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 234 269 ;; lr def 0 [$0] 1 [$1] 2 [$2] 3 [$3] 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 12 [$12] 13 [$13] 14 [$14] 15 [$15] 24 [$24] 25 [$25] 26 [$26] 27 [$27] 31 [$31] 32 [$f0] 33 [$f1] 34 [$f2] 35 [$f3] 36 [$f4] 37 [$f5] 38 [$f6] 39 [$f7] 40 [$f8] 41 [$f9] 42 [$f10] 43 [$f11] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 52 [$f20] 53 [$f21] 54 [$f22] 55 [$f23] 64 [hi] 65 [lo] 66 [] 67 [$fcc0] 68 [$fcc1] 69 [$fcc2] 70 [$fcc3] 71 [$fcc4] 72 [$fcc5] 73 [$fcc6] 74 [$fcc7] 75 [] 76 [$cprestore] 79 [$fakec] 176 [$ac1hi] 177 [$ac1lo] 178 [$ac2hi] 179 [$ac2lo] 180 [$ac3hi] 181 [$ac3lo] 283 284 285 ;; live in 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] 234 269 ;; live gen 2 [$2] 4 [$4] 5 [$5] 6 [$6] 79 [$fakec] 283 284 285 ;; live kill 31 [$31] ;; rd in (49) 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 37, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 86, 93, 94, 95, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 119, 120, 121 ;; rd gen (5) 2, 85, 116, 117, 118 ;; rd kill (9) 2, 3, 36, 37, 85, 86, 116, 117, 118 ;; lr out 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live out 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 79 [$fakec] ;; rd out (52) 2, 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 85, 93, 94, 95, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121 ;; UD chains for artificial uses ;; reg 28 { d33(bb 0 insn -1) } ;; reg 29 { d34(bb 0 insn -1) } ;; reg 30 { d35(bb 0 insn -1) } ;; reg 77 { d83(bb 0 insn -1) } ;; reg 78 { d84(bb 0 insn -1) } ;; UD chains for insn luid 0 uid 79 ;; reg 269 { d104(bb 2 insn 45) } ;; UD chains for insn luid 1 uid 80 ;; reg 283 { d116(bb 6 insn 79) } ;; UD chains for insn luid 3 uid 82 ;; reg 285 { d118(bb 6 insn 81) } ;; UD chains for insn luid 6 uid 85 ;; reg 29 { d34(bb 0 insn -1) } ;; reg 4 { d6(bb 6 insn 82) } ;; reg 5 { d9(bb 6 insn 83) } ;; reg 6 { d12(bb 6 insn 84) } ;; reg 79 { d86(bb 0 insn -1) } ;; reg 284 { d117(bb 6 insn 80) } ;; UD chains for insn luid 7 uid 86 ;; reg 79 { d86(bb 0 insn -1) } ;; UD chains for insn luid 8 uid 91 ;; reg 234 { d94(bb 5 insn 76) d93(bb 2 insn 48) } ;; UD chains for insn luid 9 uid 94 ;; reg 2 { d2(bb 6 insn 91) } ( 6 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u74(2){ d2(bb 6 insn 91) }u75(28){ d33(bb 0 insn -1) }u76(29){ d34(bb 0 insn -1) }u77(30){ d35(bb 0 insn -1) }u78(31){ }u79(78){ d84(bb 0 insn -1) }u80(79){ d85(bb 6 insn 86) }} ;; lr in 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 78 [$frame] 79 [$fakec] ;; lr use 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 78 [$frame] 79 [$fakec] ;; lr def ;; live in 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 78 [$frame] 79 [$fakec] ;; live gen ;; live kill ;; rd in (52) 2, 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 85, 93, 94, 95, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121 ;; rd gen (0) ;; rd kill (0) ;; lr out ;; live out ;; rd out (52) 2, 7, 10, 13, 15, 17, 19, 21, 23, 30, 33, 34, 35, 51, 53, 55, 57, 59, 61, 63, 65, 83, 84, 85, 93, 94, 95, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121 ;; UD chains for artificial uses ;; reg 2 { d2(bb 6 insn 91) } ;; reg 28 { d33(bb 0 insn -1) } ;; reg 29 { d34(bb 0 insn -1) } ;; reg 30 { d35(bb 0 insn -1) } ;; reg 31 { } ;; reg 78 { d84(bb 0 insn -1) } ;; reg 79 { d85(bb 6 insn 86) } Finding needed instructions: Adding insn 52 to worklist Adding insn 71 to worklist Adding insn 68 to worklist Adding insn 94 to worklist Adding insn 85 to worklist Finished finding needed instructions: Adding insn 91 to worklist Adding insn 86 to worklist Processing use of (reg 79 $fakec) in insn 86: Processing use of (reg 234 [ count+-4 ]) in insn 91: Adding insn 76 to worklist Adding insn 48 to worklist Processing use of (reg 282) in insn 76: Adding insn 75 to worklist Processing use of (reg 281) in insn 75: Adding insn 74 to worklist Processing use of (subreg (reg 257 [ D.2064+-4 ]) 4) in insn 74: Adding insn 54 to worklist Processing use of (reg 280) in insn 74: Adding insn 73 to worklist Processing use of (subreg (reg 264 [ start+-4 ]) 4) in insn 73: Adding insn 40 to worklist Processing use of (reg 4 $4) in insn 40: Processing use of (subreg (reg 265 [ end+-4 ]) 4) in insn 54: Adding insn 41 to worklist Processing use of (reg 5 $5) in insn 41: Processing use of (reg 29 $sp) in insn 85: Processing use of (reg 4 $4) in insn 85: Adding insn 82 to worklist Processing use of (reg 5 $5) in insn 85: Adding insn 83 to worklist Processing use of (reg 6 $6) in insn 85: Adding insn 84 to worklist Processing use of (reg 79 $fakec) in insn 85: Processing use of (reg 284 [ D.2020_21->vp ]) in insn 85: Adding insn 80 to worklist Processing use of (reg 283 [ sp_20(D)->s ]) in insn 80: Adding insn 79 to worklist Processing use of (reg 269 [ sp ]) in insn 79: Adding insn 45 to worklist Processing use of (reg 9 $9) in insn 45: Processing use of (reg 285) in insn 82: Adding insn 81 to worklist Processing use of (reg 2 $2) in insn 94: Processing use of (reg 275) in insn 68: Adding insn 63 to worklist Processing use of (reg 279) in insn 68: Adding insn 67 to worklist Processing use of (subreg (reg 268 [ c+-4 ]) 4) in insn 67: Adding insn 44 to worklist Processing use of (reg 278 [ MEM[base: D.2059_48, offset: 0B] ]) in insn 67: Adding insn 66 to worklist Processing use of (reg 277) in insn 66: Adding insn 65 to worklist Processing use of (reg 250 [ ivtmp.16 ]) in insn 65: Adding insn 47 to worklist Adding insn 69 to worklist Processing use of (reg 289) in insn 65: Adding insn 64 to worklist Processing use of (reg 267 [ b ]) in insn 64: Adding insn 43 to worklist Processing use of (reg 287 [ D.2057 ]) in insn 64: Adding insn 103 to worklist Processing use of (reg 264 [ start+-4 ]) in insn 103: Processing use of (reg 7 $7) in insn 43: Processing use of (reg 250 [ ivtmp.16 ]) in insn 69: Processing use of (reg 8 $8) in insn 44: Processing use of (reg 250 [ ivtmp.16 ]) in insn 63: Processing use of (reg 288) in insn 63: Adding insn 62 to worklist Processing use of (reg 266 [ a ]) in insn 62: Adding insn 42 to worklist Processing use of (reg 287 [ D.2057 ]) in insn 62: Processing use of (reg 6 $6) in insn 42: Processing use of (reg 250 [ ivtmp.16 ]) in insn 71: Processing use of (reg 262 [ D.2069 ]) in insn 71: Adding insn 58 to worklist Processing use of (reg 273) in insn 58: Adding insn 57 to worklist Processing use of (reg 272) in insn 57: Adding insn 56 to worklist Processing use of (reg 271) in insn 56: Adding insn 55 to worklist Processing use of (subreg (reg 257 [ D.2064+-4 ]) 4) in insn 55: Processing use of (subreg (reg 264 [ start+-4 ]) 4) in insn 55: Processing use of (reg 270) in insn 52: Adding insn 51 to worklist Processing use of (subreg (reg 264 [ start+-4 ]) 4) in insn 51: Processing use of (subreg (reg 265 [ end+-4 ]) 4) in insn 51: (note 49 0 40 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (insn 40 49 41 2 (set (reg/v:DI 264 [ start+-4 ]) (reg:DI 4 $4 [ start+-4 ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:34 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 4 $4 [ start+-4 ]) (nil))) (insn 41 40 42 2 (set (reg/v:DI 265 [ end+-4 ]) (reg:DI 5 $5 [ end+-4 ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:34 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 5 $5 [ end+-4 ]) (nil))) (insn 42 41 43 2 (set (reg/v/f:DI 266 [ a ]) (reg:DI 6 $6 [ a ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:34 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 6 $6 [ a ]) (nil))) (insn 43 42 44 2 (set (reg/v/f:DI 267 [ b ]) (reg:DI 7 $7 [ b ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:34 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 7 $7 [ b ]) (nil))) (insn 44 43 45 2 (set (reg/v:DI 268 [ c+-4 ]) (reg:DI 8 $8 [ c+-4 ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:34 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 8 $8 [ c+-4 ]) (nil))) (insn 45 44 46 2 (set (reg/v/f:DI 269 [ sp ]) (reg:DI 9 $9 [ sp ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:34 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 9 $9 [ sp ]) (nil))) (note 46 45 51 2 NOTE_INSN_FUNCTION_BEG) (insn 51 46 48 2 (set (reg:SI 270) (gt:SI (subreg/s:SI (reg/v:DI 264 [ start+-4 ]) 4) (subreg/s:SI (reg/v:DI 265 [ end+-4 ]) 4))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 460 {*sgt_sisi} (nil)) (insn 48 51 52 2 (set (reg/v:DI 234 [ count+-4 ]) (const_int 0 [0])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:35 276 {*movdi_64bit} (nil)) (jump_insn 52 48 53 2 (set (pc) (if_then_else (ne (reg:SI 270) (const_int 0 [0])) (label_ref:DI 77) (pc))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 426 {*branch_equalitysi} (expr_list:REG_DEAD (reg:SI 270) (expr_list:REG_BR_PROB (const_int 900 [0x384]) (nil))) -> 77) (note 53 52 54 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 54 53 55 3 (set (reg:DI 257 [ D.2064+-4 ]) (sign_extend:DI (subreg:SI (reg/v:DI 265 [ end+-4 ]) 4))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 202 {extendsidi2} (expr_list:REG_DEAD (reg/v:DI 265 [ end+-4 ]) (nil))) (insn 55 54 56 3 (set (reg:SI 271) (minus:SI (subreg/s:SI (reg:DI 257 [ D.2064+-4 ]) 4) (subreg:SI (reg/v:DI 264 [ start+-4 ]) 4))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 23 {subsi3} (nil)) (insn 56 55 57 3 (set (reg:DI 272) (zero_extend:DI (reg:SI 271))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 181 {*zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 271) (nil))) (insn 57 56 58 3 (set (reg:DI 273) (plus:DI (reg:DI 272) (const_int 1 [0x1]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (expr_list:REG_DEAD (reg:DI 272) (nil))) (insn 58 57 47 3 (set (reg:DI 262 [ D.2069 ]) (ashift:DI (reg:DI 273) (const_int 2 [0x2]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 405 {*ashldi3} (expr_list:REG_DEAD (reg:DI 273) (nil))) (insn 47 58 103 3 (set (reg:DI 250 [ ivtmp.16 ]) (const_int 0 [0])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 276 {*movdi_64bit} (nil)) (insn 103 47 62 3 (set (reg:DI 287 [ D.2057 ]) (ashift:DI (reg/v:DI 264 [ start+-4 ]) (const_int 2 [0x2]))) 405 {*ashldi3} (nil)) (insn 62 103 64 3 (set (reg:DI 288) (plus:DI (reg/v/f:DI 266 [ a ]) (reg:DI 287 [ D.2057 ]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (expr_list:REG_DEAD (reg/v/f:DI 266 [ a ]) (nil))) (insn 64 62 70 3 (set (reg:DI 289) (plus:DI (reg/v/f:DI 267 [ b ]) (reg:DI 287 [ D.2057 ]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (expr_list:REG_DEAD (reg:DI 287 [ D.2057 ]) (expr_list:REG_DEAD (reg/v/f:DI 267 [ b ]) (nil)))) (code_label 70 64 59 4 3 "" [1 uses]) (note 59 70 63 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 63 59 65 4 (set (reg:DI 275) (plus:DI (reg:DI 288) (reg:DI 250 [ ivtmp.16 ]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (nil)) (insn 65 63 66 4 (set (reg:DI 277) (plus:DI (reg:DI 289) (reg:DI 250 [ ivtmp.16 ]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (nil)) (insn 66 65 67 4 (set (reg:SI 278 [ MEM[base: D.2059_48, offset: 0B] ]) (mem:SI (reg:DI 277) [2 MEM[base: D.2059_48, offset: 0B]+0 S4 A32])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 278 {*movsi_internal} (expr_list:REG_DEAD (reg:DI 277) (nil))) (insn 67 66 68 4 (set (reg:SI 279) (plus:SI (reg:SI 278 [ MEM[base: D.2059_48, offset: 0B] ]) (subreg/s:SI (reg/v:DI 268 [ c+-4 ]) 4))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 10 {*addsi3} (expr_list:REG_DEAD (reg:SI 278 [ MEM[base: D.2059_48, offset: 0B] ]) (nil))) (insn 68 67 69 4 (set (mem:SI (reg:DI 275) [2 MEM[base: D.2063_52, offset: 0B]+0 S4 A32]) (reg:SI 279)) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 278 {*movsi_internal} (expr_list:REG_DEAD (reg:SI 279) (expr_list:REG_DEAD (reg:DI 275) (nil)))) (insn 69 68 71 4 (set (reg:DI 250 [ ivtmp.16 ]) (plus:DI (reg:DI 250 [ ivtmp.16 ]) (const_int 4 [0x4]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 11 {*adddi3} (nil)) (jump_insn 71 69 72 4 (set (pc) (if_then_else (ne (reg:DI 250 [ ivtmp.16 ]) (reg:DI 262 [ D.2069 ])) (label_ref:DI 70) (pc))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 427 {*branch_equalitydi} (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil)) -> 70) (note 72 71 73 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (insn 73 72 74 5 (set (reg:SI 280) (not:SI (subreg/s:SI (reg/v:DI 264 [ start+-4 ]) 4))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 149 {one_cmplsi2} (expr_list:REG_DEAD (reg/v:DI 264 [ start+-4 ]) (nil))) (insn 74 73 75 5 (set (reg:SI 281) (plus:SI (reg:SI 280) (subreg/s:SI (reg:DI 257 [ D.2064+-4 ]) 4))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 10 {*addsi3} (expr_list:REG_DEAD (reg:SI 280) (expr_list:REG_DEAD (reg:DI 257 [ D.2064+-4 ]) (nil)))) (insn 75 74 76 5 (set (reg:SI 282) (plus:SI (reg:SI 281) (const_int 2 [0x2]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 10 {*addsi3} (expr_list:REG_DEAD (reg:SI 281) (nil))) (insn 76 75 77 5 (set (reg/v:DI 234 [ count+-4 ]) (sign_extend:DI (reg:SI 282))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 202 {extendsidi2} (expr_list:REG_DEAD (reg:SI 282) (nil))) (code_label 77 76 78 6 2 "" [1 uses]) (note 78 77 79 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (insn 79 78 80 6 (set (reg/f:DI 283 [ sp_20(D)->s ]) (mem/s/f:DI (plus:DI (reg/v/f:DI 269 [ sp ]) (const_int 16 [0x10])) [4 sp_20(D)->s+0 S8 A64])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 276 {*movdi_64bit} (expr_list:REG_DEAD (reg/v/f:DI 269 [ sp ]) (nil))) (insn 80 79 81 6 (set (reg/f:DI 284 [ D.2020_21->vp ]) (mem/s/f:DI (plus:DI (reg/f:DI 283 [ sp_20(D)->s ]) (const_int 8 [0x8])) [4 D.2020_21->vp+0 S8 A64])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 276 {*movdi_64bit} (expr_list:REG_DEAD (reg/f:DI 283 [ sp_20(D)->s ]) (nil))) (insn 81 80 82 6 (set (reg/f:DI 285) (high:DI (symbol_ref/f:DI ("*.LC0") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 265 {*got_pagedi} (nil)) (insn 82 81 83 6 (set (reg:DI 4 $4) (lo_sum:DI (reg/f:DI 285) (symbol_ref/f:DI ("*.LC0") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 269 {*lowdi} (expr_list:REG_DEAD (reg/f:DI 285) (expr_list:REG_EQUAL (symbol_ref/f:DI ("*.LC0") [flags 0x2] ) (nil)))) (insn 83 82 84 6 (set (reg:DI 5 $5) (symbol_ref:DI ("exit") [flags 0x41] )) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 263 {*got_dispdi} (nil)) (insn 84 83 85 6 (set (reg:DI 6 $6) (symbol_ref:DI ("M_var") [flags 0x2] )) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 263 {*got_dispdi} (nil)) (call_insn 85 84 86 6 (parallel [ (set (reg:DI 2 $2) (call (mem:SI (reg/f:DI 284 [ D.2020_21->vp ]) [0 S4 A32]) (const_int 0 [0]))) (clobber (reg:SI 31 $31)) ]) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 570 {call_value_internal} (expr_list:REG_DEAD (reg/f:DI 284 [ D.2020_21->vp ]) (expr_list:REG_DEAD (reg:DI 6 $6) (expr_list:REG_DEAD (reg:DI 5 $5) (expr_list:REG_DEAD (reg:DI 4 $4) (expr_list:REG_UNUSED (reg:DI 2 $2) (nil)))))) (expr_list:REG_DEP_TRUE (use (reg:DI 79 $fakec)) (expr_list:REG_DEP_TRUE (use (reg:DI 6 $6)) (expr_list:REG_DEP_TRUE (use (reg:DI 5 $5)) (expr_list:REG_DEP_TRUE (use (reg:DI 4 $4)) (nil)))))) (insn 86 85 91 6 (set (reg:SI 79 $fakec) (unspec:SI [ (reg:SI 79 $fakec) ] UNSPEC_UPDATE_GOT_VERSION)) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 562 {update_got_version} (nil)) (insn 91 86 94 6 (set (reg/i:DI 2 $2) (reg/v:DI 234 [ count+-4 ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:45 276 {*movdi_64bit} (expr_list:REG_DEAD (reg/v:DI 234 [ count+-4 ]) (nil))) (insn 94 91 0 6 (use (reg/i:DI 2 $2)) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:45 -1 (nil)) starting the processing of deferred insns ending the processing of deferred insns ;; Function g (g) starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) g Dataflow summary: ;; invalidated by call 0 [$0] 1 [$1] 2 [$2] 3 [$3] 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 12 [$12] 13 [$13] 14 [$14] 15 [$15] 24 [$24] 25 [$25] 26 [$26] 27 [$27] 32 [$f0] 33 [$f1] 34 [$f2] 35 [$f3] 36 [$f4] 37 [$f5] 38 [$f6] 39 [$f7] 40 [$f8] 41 [$f9] 42 [$f10] 43 [$f11] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 52 [$f20] 53 [$f21] 54 [$f22] 55 [$f23] 64 [hi] 65 [lo] 66 [] 67 [$fcc0] 68 [$fcc1] 69 [$fcc2] 70 [$fcc3] 71 [$fcc4] 72 [$fcc5] 73 [$fcc6] 74 [$fcc7] 75 [] 76 [$cprestore] 176 [$ac1hi] 177 [$ac1lo] 178 [$ac2hi] 179 [$ac2lo] 180 [$ac3hi] 181 [$ac3lo] ;; hardware regs used 28 [$28] 29 [$sp] 77 [$arg] 78 [$frame] ;; regular block artificial uses 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] ;; eh block artificial uses 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] ;; entry block defs 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 25 [$25] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 77 [$arg] 78 [$frame] 79 [$fakec] ;; exit block uses 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 78 [$frame] 79 [$fakec] ;; regs ever live 2[$2] 4[$4] ;; ref usage r2={1d,2u} r4={1d,1u} r5={1d} r6={1d} r7={1d} r8={1d} r9={1d} r10={1d} r11={1d} r25={1d} r28={1d,4u} r29={1d,4u} r30={1d,4u} r31={1d,1u} r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r50={1d} r51={1d} r77={1d,3u} r78={1d,4u} r79={1d,1u} r194={2d,1u} r198={1d,1u} r199={1d,2u} r200={1d,1u} r201={1d,1u} r202={1d,1u} r203={1d,1u} r204={1d,1u} r205={1d,1u} ;; total ref usage 69{35d,34u,0e} in 13{13 regular + 0 call} insns. ;; Reaching defs: sparse invalidated dense invalidated 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 17, 18, 19, 20, 21 2[0,1] 4[1,1] 5[2,1] 6[3,1] 7[4,1] 8[5,1] 9[6,1] 10[7,1] 11[8,1] 25[9,1] 28[10,1] 29[11,1] 30[12,1] 31[13,1] 44[14,1] 45[15,1] 46[16,1] 47[17,1] 48[18,1] 49[19,1] 50[20,1] 51[21,1] 77[22,1] 78[23,1] 79[24,1] 194[25,2] 198[27,1] 199[28,1] 200[29,1] 201[30,1] 202[31,1] 203[32,1] 204[33,1] 205[34,1] ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d1(4){ }d2(5){ }d3(6){ }d4(7){ }d5(8){ }d6(9){ }d7(10){ }d8(11){ }d9(25){ }d10(28){ }d11(29){ }d12(30){ }d13(31){ }d14(44){ }d15(45){ }d16(46){ }d17(47){ }d18(48){ }d19(49){ }d20(50){ }d21(51){ }d22(77){ }d23(78){ }d24(79){ }} ;; bb 0 artificial_uses: { } ;; lr in ;; lr use ;; lr def 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 25 [$25] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live in ;; live gen 4 [$4] 5 [$5] 6 [$6] 7 [$7] 8 [$8] 9 [$9] 10 [$10] 11 [$11] 25 [$25] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 44 [$f12] 45 [$f13] 46 [$f14] 47 [$f15] 48 [$f16] 49 [$f17] 50 [$f18] 51 [$f19] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live kill ;; rd in (0) ;; rd gen (24) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ;; rd kill (24) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ;; lr out 4 [$4] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live out 4 [$4] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] ;; rd out (24) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ( 0 )->[2]->( 4 3 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u0(28){ d10(bb 0 insn -1) }u1(29){ d11(bb 0 insn -1) }u2(30){ d12(bb 0 insn -1) }u3(77){ d22(bb 0 insn -1) }u4(78){ d23(bb 0 insn -1) }} ;; lr in 4 [$4] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] ;; lr use 4 [$4] 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] ;; lr def 194 198 199 200 ;; live in 4 [$4] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live gen 194 198 199 200 ;; live kill ;; rd in (24) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ;; rd gen (4) 25, 27, 28, 29 ;; rd kill (5) 25, 26, 27, 28, 29 ;; lr out 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 194 199 ;; live out 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 194 199 ;; rd out (28) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29 ;; UD chains for artificial uses ;; reg 28 { d10(bb 0 insn -1) } ;; reg 29 { d11(bb 0 insn -1) } ;; reg 30 { d12(bb 0 insn -1) } ;; reg 77 { d22(bb 0 insn -1) } ;; reg 78 { d23(bb 0 insn -1) } ;; UD chains for insn luid 0 uid 2 ;; reg 4 { d1(bb 0 insn -1) } ;; UD chains for insn luid 1 uid 7 ;; reg 198 { d27(bb 2 insn 2) } ;; UD chains for insn luid 2 uid 9 ;; reg 199 { d28(bb 2 insn 7) } ;; UD chains for insn luid 4 uid 10 ;; reg 200 { d29(bb 2 insn 9) } ( 2 )->[3]->( 4 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u9(28){ d10(bb 0 insn -1) }u10(29){ d11(bb 0 insn -1) }u11(30){ d12(bb 0 insn -1) }u12(77){ d22(bb 0 insn -1) }u13(78){ d23(bb 0 insn -1) }} ;; lr in 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 199 ;; lr use 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 199 ;; lr def 194 201 202 203 204 205 ;; live in 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 199 ;; live gen 194 201 202 203 204 205 ;; live kill ;; rd in (28) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29 ;; rd gen (6) 26, 30, 31, 32, 33, 34 ;; rd kill (7) 25, 26, 30, 31, 32, 33, 34 ;; lr out 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 194 ;; live out 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 194 ;; rd out (33) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, 32, 33, 34 ;; UD chains for artificial uses ;; reg 28 { d10(bb 0 insn -1) } ;; reg 29 { d11(bb 0 insn -1) } ;; reg 30 { d12(bb 0 insn -1) } ;; reg 77 { d22(bb 0 insn -1) } ;; reg 78 { d23(bb 0 insn -1) } ;; UD chains for insn luid 1 uid 13 ;; reg 199 { d28(bb 2 insn 7) } ;; UD chains for insn luid 2 uid 14 ;; reg 202 { d31(bb 3 insn 13) } ;; UD chains for insn luid 3 uid 15 ;; reg 201 { d30(bb 3 insn 12) } ;; UD chains for insn luid 4 uid 16 ;; reg 203 { d32(bb 3 insn 14) } ;; reg 205 { d34(bb 3 insn 15) } ;; UD chains for insn luid 5 uid 17 ;; reg 204 { d33(bb 3 insn 16) } ( 2 3 )->[4]->( 1 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u20(28){ d10(bb 0 insn -1) }u21(29){ d11(bb 0 insn -1) }u22(30){ d12(bb 0 insn -1) }u23(77){ d22(bb 0 insn -1) }u24(78){ d23(bb 0 insn -1) }} ;; lr in 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 194 ;; lr use 28 [$28] 29 [$sp] 30 [$fp] 77 [$arg] 78 [$frame] 194 ;; lr def 2 [$2] ;; live in 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] 194 ;; live gen 2 [$2] ;; live kill ;; rd in (34) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 ;; rd gen (1) 0 ;; rd kill (1) 0 ;; lr out 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] ;; live out 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 77 [$arg] 78 [$frame] 79 [$fakec] ;; rd out (35) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 ;; UD chains for artificial uses ;; reg 28 { d10(bb 0 insn -1) } ;; reg 29 { d11(bb 0 insn -1) } ;; reg 30 { d12(bb 0 insn -1) } ;; reg 77 { d22(bb 0 insn -1) } ;; reg 78 { d23(bb 0 insn -1) } ;; UD chains for insn luid 0 uid 24 ;; reg 194 { d26(bb 3 insn 17) d25(bb 2 insn 4) } ;; UD chains for insn luid 1 uid 27 ;; reg 2 { d0(bb 4 insn 24) } ( 4 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u27(2){ d0(bb 4 insn 24) }u28(28){ d10(bb 0 insn -1) }u29(29){ d11(bb 0 insn -1) }u30(30){ d12(bb 0 insn -1) }u31(31){ d13(bb 0 insn -1) }u32(78){ d23(bb 0 insn -1) }u33(79){ d24(bb 0 insn -1) }} ;; lr in 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 78 [$frame] 79 [$fakec] ;; lr use 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 78 [$frame] 79 [$fakec] ;; lr def ;; live in 2 [$2] 28 [$28] 29 [$sp] 30 [$fp] 31 [$31] 78 [$frame] 79 [$fakec] ;; live gen ;; live kill ;; rd in (35) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 ;; rd gen (0) ;; rd kill (0) ;; lr out ;; live out ;; rd out (35) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 ;; UD chains for artificial uses ;; reg 2 { d0(bb 4 insn 24) } ;; reg 28 { d10(bb 0 insn -1) } ;; reg 29 { d11(bb 0 insn -1) } ;; reg 30 { d12(bb 0 insn -1) } ;; reg 31 { d13(bb 0 insn -1) } ;; reg 78 { d23(bb 0 insn -1) } ;; reg 79 { d24(bb 0 insn -1) } Finding needed instructions: Adding insn 10 to worklist Adding insn 27 to worklist Finished finding needed instructions: Adding insn 24 to worklist Processing use of (reg 194 [ D.2012+-4 ]) in insn 24: Adding insn 17 to worklist Adding insn 4 to worklist Processing use of (reg 204) in insn 17: Adding insn 16 to worklist Processing use of (reg 203) in insn 16: Adding insn 14 to worklist Processing use of (reg 205) in insn 16: Adding insn 15 to worklist Processing use of (reg 201) in insn 15: Adding insn 12 to worklist Processing use of (reg 202 [ csui.0+-4 ]) in insn 14: Adding insn 13 to worklist Processing use of (reg 199) in insn 13: Adding insn 7 to worklist Processing use of (subreg (reg 198 [ i+-4 ]) 4) in insn 7: Adding insn 2 to worklist Processing use of (reg 4 $4) in insn 2: Processing use of (reg 2 $2) in insn 27: Processing use of (reg 200) in insn 10: Adding insn 9 to worklist Processing use of (reg 199) in insn 9: (note 5 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (insn 2 5 3 2 (set (reg/v:DI 198 [ i+-4 ]) (reg:DI 4 $4 [ i+-4 ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:49 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 4 $4 [ i+-4 ]) (nil))) (note 3 2 7 2 NOTE_INSN_FUNCTION_BEG) (insn 7 3 9 2 (set (reg:SI 199) (plus:SI (subreg:SI (reg/v:DI 198 [ i+-4 ]) 4) (const_int -1 [0xffffffffffffffff]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 10 {*addsi3} (expr_list:REG_DEAD (reg/v:DI 198 [ i+-4 ]) (nil))) (insn 9 7 4 2 (set (reg:SI 200) (leu:SI (reg:SI 199) (const_int 4 [0x4]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 501 {*sleu_sisi} (nil)) (insn 4 9 10 2 (set (reg:DI 194 [ D.2012+-4 ]) (const_int 0 [0])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 276 {*movdi_64bit} (nil)) (jump_insn 10 4 11 2 (set (pc) (if_then_else (eq (reg:SI 200) (const_int 0 [0])) (label_ref:DI 18) (pc))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 426 {*branch_equalitysi} (expr_list:REG_DEAD (reg:SI 200) (expr_list:REG_BR_PROB (const_int 3900 [0xf3c]) (nil))) -> 18) (note 11 10 12 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 12 11 13 3 (set (reg/f:DI 201) (high:DI (symbol_ref:DI ("CSWTCH.1") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 265 {*got_pagedi} (nil)) (insn 13 12 14 3 (set (reg:DI 202 [ csui.0+-4 ]) (zero_extend:DI (reg:SI 199))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 181 {*zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 199) (nil))) (insn 14 13 15 3 (set (reg:DI 203) (ashift:DI (reg:DI 202 [ csui.0+-4 ]) (const_int 2 [0x2]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 405 {*ashldi3} (expr_list:REG_DEAD (reg:DI 202 [ csui.0+-4 ]) (nil))) (insn 15 14 16 3 (set (reg/f:DI 205) (lo_sum:DI (reg/f:DI 201) (symbol_ref:DI ("CSWTCH.1") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 269 {*lowdi} (expr_list:REG_DEAD (reg/f:DI 201) (expr_list:REG_EQUAL (symbol_ref:DI ("CSWTCH.1") [flags 0x2] ) (nil)))) (insn 16 15 17 3 (set (reg/f:DI 204) (plus:DI (reg:DI 203) (reg/f:DI 205))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 11 {*adddi3} (expr_list:REG_DEAD (reg/f:DI 205) (expr_list:REG_DEAD (reg:DI 203) (nil)))) (insn 17 16 18 3 (set (reg:DI 194 [ D.2012+-4 ]) (sign_extend:DI (mem/s/u:SI (reg/f:DI 204) [2 CSWTCH.1 S4 A32]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 202 {extendsidi2} (expr_list:REG_DEAD (reg/f:DI 204) (nil))) (code_label 18 17 19 4 8 "" [1 uses]) (note 19 18 24 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 24 19 27 4 (set (reg/i:DI 2 $2) (reg:DI 194 [ D.2012+-4 ])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:59 276 {*movdi_64bit} (expr_list:REG_DEAD (reg:DI 194 [ D.2012+-4 ]) (nil))) (insn 27 24 0 4 (use (reg/i:DI 2 $2)) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:59 -1 (nil)) starting the processing of deferred insns ending the processing of deferred insns