*** IDEA A ***

12 opcodes = 4 bits each using 12/16 possible codes leaving 4 blanks
64 regs = 6 bits each using 64/64 possible values

instruction = 32 bits

instruction = opcode + reg + reg + reg
			= 4 bits + 6 bits + 6 bits + 6 bits
			= 22 bits

22/32 bits used, leaving 10 blanks

May as well pad with leading zeroes for blanks in instructions.

ADD32 = 0 0 0 0
ADD8  = 0 0 0 1
MULT  = 0 0 1 0

AND   = 0 0 1 1
OR    = 0 1 0 0
NOT   = 0 1 0 1

SLL   = 0 1 1 0

LD32  = 0 1 1 1
ST32  = 1 0 0 0

EQ    = 1 0 0 1
GT    = 1 0 1 0
JMP   = 1 0 1 1

XXX   = 1 1 0 0
XXX   = 1 1 0 1
XXX   = 1 1 1 0
XXX   = 1 1 1 1

Add8 rg[1] to rg[2] and store result in rg[3]
0 0 0 0 0 0 0 0 0 0 [0 0 0 1] [0 0 0 0 0 1] [0 0 0 0 1 0] [0 0 0 0 1 1]

May as well use big endian for memory as it will probably avoid confusion

PC is incremented by 4 after each instruction (each instruction uses 4 bytes)

Any harm in using 1 byte per instruction and register? Will lead to more zero padding elsewhere but will simplify design.

*** IDEA B ***

12 opcodes = 1 byte each

ADD32 = 0 0 0 0 0 0 0 0
ADD8  = 0 0 0 0 0 0 0 1
MULT  = 0 0 0 0 0 0 1 0

AND   = 0 0 0 0 0 0 1 1
OR    = 0 0 0 0 0 1 0 0
NOT   = 0 0 0 0 0 1 0 1

SLL   = 0 0 0 0 0 1 1 0

LD32  = 0 0 0 0 0 1 1 1
ST32  = 0 0 0 0 1 0 0 0

EQ    = 0 0 0 0 1 0 0 1
GT    = 0 0 0 0 1 0 1 0
JMP   = 0 0 0 0 1 0 1 1

64 registers = 1 byte each

Add8 rg[1] to rg[2] and store result in rg[3]
[0 0 0 0 0 0 0 1] [0 0 0 0 0 0 0 1] [0 0 0 0 0 0 1 0] [0 0 0 0 0 0 1 1]

Simpler to parse instructions but more time-consuming to write programs.